Sub-half micron multilevel metallization is a very important technology for the next generation of very large scale integration ("VLSI"). The multilevel features, including contacts, vias, lines and the like, that lie at the heart of VLSI technology must be reliably formed at increasing circuit densities. One means for increasing circuit density is to decrease the dimensions of the metal conductors that make up the integrated circuit. As the dimensions are made smaller, the operating speed increases and the power density remains constant, but the current density is increased in proportion to the scale-down factor. Therefore, as feature sizes decrease, it is increasingly important that the metal features have high electrical conductivity.
The electrical conductivity of metal features in an integrated circuit can be effected by a number of phenomena, depending upon the design of the circuit and the fabrication techniques used. For example, electromigration is a diffusive process in which the atoms of a solid move from one place to another under the influence of electrical forces. This effect limits the maximum current that can be carried by a conductor without its rapid destruction. For aluminum conductors of integrated circuits, the current density should be kept lower than about 10.sup.6 A/cm2. While electromigration does not limit the minimum device size, it limits the number of circuit functions that can be carried out by a given number of connected circuit elements per unit time. However, conductors with highly oriented crystalline structures exhibit enhanced resistance to electromigration. Therefore, as geometries of integrated circuits are reduced, the need for highly oriented films increases. Ideally, an aluminum film layer having a &lt;111&gt; crystal orientation is formed on the substrate to improve the electromigration resistance of the film at these small geometries. Typically, a Ti underlayer is used to improve the &lt;111&gt; crystal orientation of Al.
Another phenomena that effects electrical conductivity of metals is the formation of an electrically resistive layer of TiAl.sub.3 caused by the interaction of titanium (Ti) and aluminum (Al) layers. TiAl.sub.3 is believed to increase electrical resistance, especially in smaller feature sizes, such as sub quarter micron vias. The formation of TiAl.sub.3 is also believed to be disadvantageous for stress migration and etching of the film. However, both titanium and aluminum are conductive metals that are commonly used in the formation of conductive metal devices within integrated circuits. The unique physical properties of both titanium and aluminum are beneficially used in various combinations to produce devices that are superior to those made without the combination. Therefore, it is most beneficial to find ways to minimize or prevent their interaction.
Titanium is known to be useful as a "glue" layer between a silicon or silicon dioxide layer and conductive metal layers such as aluminum. As the term "glue" layer implies, the titanium adheres to the silicon better than many other conductive metals, such as aluminum, and also forms a strong bond with adjacent conductive metals.
Aluminum is known to be useful for forming conductive metal lines and features throughout an integrated circuit due to its high electrical conductivity and good processability. Aluminum may be deposited by various techniques including both physical vapor deposition (PVD) and chemical vapor deposition (CVD). However, aluminum is also known to invade the structure of silicon which may cause device failure, and it can experience electromigration at high current densities. Aluminum spiking is minimized by the use of a continuous barrier layer, such as Ti or TiN, between aluminum and silicon layers. The electromigration resistance of aluminum is increased by forming highly crystalline structures and/or providing an aluminum/copper alloy. Aluminum/copper alloys may be formed by depositing copper along with the aluminum, i.e., PVD Al/Cu, or doping an aluminum by subsequent deposition and diffusion of copper therein.
Ti is commonly used as a wetting layer to enable the flow of a PVD deposited Al film into vias, trenches, etc. However, TiAl.sub.3 formation increases the line and via resistance. One method for minimizing or preventing formation of electrically resistive TiAl.sub.3 is to separate titanium and aluminum layers with a layer of titanium nitride (TiN). The benefit of the TiN layer is that it provides good bonding between titanium and aluminum, yet does not interact with the aluminum. However, TiN tends to be flaky and adhere loosely to the chamber walls and can become a particle source within the chamber.
Although a deposition sequence of Ti/TiN/Al has been shown to reduce the formation of TiAl.sub.3, the sequence requires that the TiN layer cover the entire Ti layer in order to prevent any interaction with Al. Unfortunately, the inclusion of an additional, continuous layer in the metallization stack decreases the feature size. In order to keep from increasing the thickness of the metallization stack too drastically, it is common to use a layer of TiN that is very thin and may be less than continuous. When only an ultra-thin or subatomic layer of Ti is being used to nucleate CVD Al, the TiN layer must cover all the Ti to prevent TiAl.sub.3 formation and all of the Si must be covered by Ti or TiN to prevent aluminum migration/invasion into the silicon.
An additional limitation of both Ti and TiN layers is that they are conventionally deposited by PVD processes. While conventional PVD techniques are relatively inexpensive and can provide conformal coverage over a field (the upper or outer most surface of the wafer), these same techniques are not well suited for covering the wall and floor surfaces of high aspect ratio vias and other features. Consequently, a TiN layer that is continuous over the field may not be continuous within the via. A discontinuous TiN layer on a via floor is particularly troublesome, because it allows Ti and Al to interact and form electrically insulating TiAl.sub.3 across the face of contact between the metal plug and the feature.
Furthermore, even after depositing PVD Ti/TiN in the via, the via may still have areas of exposed silicon in the case of silicon contacts, particularly along the base of the via sidewalls and the perimeter edge of the via floor. The poor coverage of silicon in the via may be made worse if the via was over-etched to have an irregular or downwardly widening profile. Subsequently depositing aluminum directly on the exposed silicon will allow aluminum migration into the silicon.
It is known that the barrier properties of TiN can be enhanced by annealing or incorporating oxygen into the film. The oxygen fills the spaces between the grain boundaries of the TiN. Annealing can be carried out in a rapid thermal anneal (RTA) chamber, or by heating in an oxygen atmosphere. Oxygen treatment of TiN reduces the likelihood of spiking by providing a good barrier layer for Al.
Therefore, there is a need for a process that will prevent the interaction of aluminum with titanium and silicon. It would be desirable if the process could be performed in a conventional processing chamber, require fewer processing steps and reduce processing times. It would also be desirable if the process could reduce the thickness of a metallization stack while preventing the formation of TiAl3. It would be even further desirable if the process reduced the amount of particle generation.